Three-dimensional semiconductor memory devices and methods for fabricating the same
US10930739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.