High voltage LDMOS transistor and methods for manufacturing the same
US10930776B2 · kind B2 · utility
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20References
20Claims
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Key dates
| Filing date | May 8, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.