Low-power active bias circuit for a high impedance input
US10931281B2 · kind B2 · utility
1Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jan 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a floating state detection circuit of a node, comprising a first conductivity type MOS transistor (M1) connected between the node (N) and a first power supply line (Vss); and a second MOS transistor (M2) of conductivity type complementary to the first conductivity type, controlled by the node (N) and connected between the gate of the first transistor (M1) and a second supply line (Vdd). In addition, a third MOS transistor (M3) of the first conductivity type connected between the gate of the first transistor (M1) and the first supply line (Vss) may be controlled by the node (N).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.