Low-power programmable bandwidth continuous-time delta sigma modulator based analog to digital converter
US10931300B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Sep 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.