Chip failure detection method and device
US10931487B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/245
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide a method for detecting a failure of a chip. The method includes dividing a plurality of channels of the chip into multiple channel groups, providing an input bit stream to each channel group of the multiple channel groups and monitoring whether there is a difference between an output bit stream of each channel in the channel group and the input bit stream, and determining based on the difference whether each of the multiple channel groups is an abnormal channel group. Input bit streams provided to respective channels in a same channel group are identical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.