Hybrid method for high-speed serial link skew calibration
US10936007B2 · kind B2 · utility
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27Claims
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Key dates
| Filing date | Apr 3, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Aug 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing a clock-data skew in a serial interface. A clock signal and a data signal are received through the serial interface at first and second inputs of an exclusive OR (XOR) averaging (XOR-averaging) gate. An output of the XOR-averaging gate is determined and compared with a target value. At least one of a delay of the clock signal and a delay of the data signal is determined based on comparing the output of the XOR-averaging gate with the target value. A skew between the clock signal and the data signal is reduced by delaying at least one of the clock signal and the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.