PMIC/PMIC interface for distributed memory management implementations
US10936049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Jul 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.