FPGA logic cell with improved support for counters
US10936286B2 · kind B2 · utility
2Cited by
2References
5Claims
0Family size
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Key dates
| Filing date | Jan 8, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | May 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.