Method for tagging control information associated with a physical address, processing system and device
US10936506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a method for tagging control information associated with a physical address in a processing system, including setting a hardware tag for the control information, the hardware tag being invisible to a software system in the processing system; joining the hardware tag with the physical address to form a compound physical address, the hardware tag including M bits carried by a dedicated hardware tag control line, the physical address including N bits carried by a physical address bus, M and N being positive integers; and tagging the control information with the hardware tag in the compound physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.