Memory interface between physical and virtual address spaces
US10936509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2018 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Jul 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.