Flexible routing of network data within a programmable integrated circuit
US10936525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2020 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Apr 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.