Methods for identifying integrated circuit failures caused by reset-domain interactions
US10936774B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit failures caused by metastability related to assertion of asynchronous resets frequently escape detection before fabrication, causing design respins and severe economic loss. The numerous reset signals, flip-flops and complex logical interactions inherent in an integrated circuit cause an analysis for reset-metastability failures to be extremely noisy, reporting an unmanageable number of false failures and making early removal of failures impractical. Said noisy reporting arises because many flip-flops where reset-metastability manifests do not necessarily cause overall failure. An effective analysis of reset-metastability failures must identify all potential failures, but also must only report true failure potential. The present invention maximizes noise reduction by applying special conditions to identify flip-flops manifesting reset-metastability without causing integrated circuit failure, which can thereby be deemed safe. By reporting only true failure potential, the present invention enables efficient, robust and error-free removal of reset-related failures from an integrated circuit prior to fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.