Systems and methods of masking during high-energy implantation when fabricating wide band gap semiconductor devices
US10937869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Dec 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/052
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The subject matter disclosed herein relates to wide band gap semiconductor power devices and, more specifically, to high-energy implantation masks used in forming silicon carbide (SiC) power devices, such as charge balanced (CB) SiC power devices. An intermediate semiconductor device structure includes a SiC substrate layer having a first conductivity type and silicon carbide (SiC) epitaxial (epi) layer having the first conductivity type disposed on the SiC substrate layer. The intermediate device structure also includes a silicon high-energy implantation mask (SiHEIM) disposed directly on a first portion of the SiC epi layer and having a thickness between 5 micrometers (μm) and 20 μm. The SiHEIM is configured to block implantation of the first portion of the SiC epi layer during a high-energy implantation process having an implantation energy greater than 500 kiloelectron volts (keV).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.