Successive approximation register analog-to-digital converter
US10938402B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 29, 2020 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.