Substrate for electrical circuits and method for producing a substrate of this type
US10940671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2016 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Aug 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1126
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A substrate (1, 10) for electrical circuits, comprising at least one metal layer (2,3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2,3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a′, 6a″, 6b′, 6b″) to the metal layer (2,3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a′, 6a″, 6b′,6b″).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.