Electrical isolation in photonic integrated circuits
US10942380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/0625
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of providing electrical isolation between subsections in a waveguide structure for a photonic integrated device, the structure comprising a substrate, a buffer layer and a core layer, the buffer layer being located between the substrate and the core and comprising a dopant of a first type, the first type being either n-type or p- type, the method comprising the steps of prior to adding any layer to a side of the core layer opposite to the buffer layer: selecting at least one area to be an electrical isolation region, applying a dielectric mask to a surface of the core layer opposite to the buffer layer, with a window in the mask exposing an area of the surface corresponding to the selected electrical isolation region, implementing diffusion of a dopant of a second type, the second type being of opposite polarity to the first type, and allowing the dopant of the second type to penetrate to the substrate to form a blocking junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.