System and method for providing heterogeneous personality bitstreams on field-programmable gate arrays from a baseboard management controller
US10942766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.