System, method and apparatus for secure functions and cache line data
US10942856B2 · kind B2 · utility
2Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Sep 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0869
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system, apparatus and method for secure functions and manipulating cache line data. The method includes generating cache block addresses from a subset of bits, i.e. tag bits, of a cache address and hashing the cache block addresses with one or more secure functions that use keys to generate secure indexes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.