Dual-edge triggered ring buffer and communication system
US10942884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2018 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4256
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.