Electronic system level parallel simulation method with detection of conflicts of access to a shared memory
US10943041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2016 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Dec 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system-level parallel simulation method by means of a multi-core computer system, comprising the parallel evaluation of a plurality of concurrent processes of the simulation on a plurality of cores of the computer system and comprising a sub-method of detection of conflicts of access to a shared memory of a simulated electronic system, the sub-method being implemented by a simulation kernel executed by the computer system and comprises: a step of construction of an oriented graph representative of access to the shared memory by the processes evaluated by the concurrent processes; and a step of detection of loops in the graph; a loop being considered representative of a conflict of access to the shared memory. A computer program product for implementing such a method is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.