Shift register unit, gate drive circuit and method of driving the same
US10943552B2 · kind B2 · utility
3Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Nov 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0414
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.