Shift register unit, gate line driving circuit and driving method thereof
US10943553B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 22, 2017 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a shift register unit, a gate driving circuit and a driving method thereof, the shift register unit including: an input sub-circuit configured to provide a trigger signal received by the signal input terminal to the pull-up node; an output sub-circuit configured to output, to the signal output terminal, a pulse signal provided by the first clock signal terminal as a driving signal for scanning a gate line under control of the pull-up node; a reset sub-circuit configured to reset the pull-up node and the signal output terminal under control of the reset terminal; and an input selection sub-circuit configured to select a trigger signal to be provided to the signal input terminal according to voltage levels at first to third control terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.