Different word line programming orders in non-volatile memory for error recovery
US10943662B1 · kind B1 · utility
7Cited by
8References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 10, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.