Semiconductor devices
US10943812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Aug 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first trench on the device region, a first device isolation layer in the first trench and defining an active pattern of the device region, a second trench on the interface region, and a second device isolation layer in the second trench. The second isolation layer includes a buried dielectric pattern, a dielectric liner pattern on the buried dielectric pattern, and a first gap-fill dielectric pattern on the dielectric liner pattern. The buried dielectric pattern includes a floor segment on a floor of the second trench, and a sidewall segment on a sidewall of the second trench. The sidewall segment has a thickness different from a thickness of the floor segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.