Integrated circuits and semiconductor device including standard cell
US10943923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Sep 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/985
Abstract
A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.