Multilevel semiconductor device and structure
US10943934B2 · kind B2 · utility
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471References
20Claims
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Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Sep 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/014
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an optical waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.