High-speed and low-noise dynamic comparator

US10944390B2 · kind B2 · utility

Assignee

• NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION · CN

Inventors

• Daiguo Xu · Chongqing, CN
• Gangyi Hu · Chongqing, CN
• Ruzhang Li · Chongqing, CN
• Jian'an Wang · Chongqing, CN
• Guangbing Chen · Tangxia, CN
• Dongbing Fu · Chongqing, CN
• Shiliu Xu · Chongqing, CN
• Tao Liu · Beijing, CN
• Jie Pu · Pforzheim, DE
• Zhihua Feng · Hefei, CN

Key dates

• Filing date: Jul 18, 2018
• Grant date: Mar 9, 2021
• Expiry date: Jul 18, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/20
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.