Phase-locked loop and delay-locked loop
US10944405B2 · kind B2 · utility
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Key dates
| Filing date | Nov 13, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a phase-locked loop which alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal. When the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.