PLL capacitor swap technique and low jitter dynamic Digital Controlled Oscillator band select
US10944411B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Dec 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.