Error correction with multiple LLR-LUTS for a single read
US10944424B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Jan 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.