Methods and systems for transcoder, FEC and interleaver optimization
US10944432B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 18, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Sep 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.