Error scaling in crest factor reduction
US10944606B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2015 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Dec 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0007
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and system for error scaling for crest factor reduction (CFR) are disclosed. According to one aspect, a method for regulating peak to average power ratio (PAR) of an output signal of the CFR circuit is disclosed. In one embodiment, the method includes receiving an input signal at an input of the CFR circuit. The magnitude of the input signal is determined and clipped to a target level to produce an error signal by comparing the input signal magnitude to a threshold in a comparator. The error signal is filtered to produce a processed error signal. The filter provides a bandpass filter frequency response. The PAR of the output signal is regulated by scaling the processed error signal by an error scaling factor to achieve a target signal to noise ratio (SNR) for the output signal corresponding to a target error vector magnitude (EVM).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.