Register for at-speed scan testing

US10948538B2 · kind B2 · utility

Assignee

• NXP USA, Inc. · US

Inventors

• Shikhar Makkar · Faridabad, IN
• Dimple Aggarwal · Noida, IN
• Nitin Anand · Pune, IN
• Manmohan Rana · Ghaziabad, IN

Key dates

• Filing date: Jun 9, 2019
• Grant date: Mar 16, 2021
• Expiry date: Jul 12, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C19/28
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit (IC) has scan chains of stitched registers that support scan testing of functional logic. The scan testing has a shift phase in which incoming and outgoing data are shifted into and out of the registers using a slow clock and a capture phase in which outgoing data from the functional logic is captured by the registers using launch-and-capture pulses of a fast clock to check for delay faults. During a warm-up period after termination of the slow clock but before application of the launch-and-capture pulses, the registers propagate data through their master latches without affecting the data stored in their slave latches. A warm-up controller configures the registers and generates control signals to perform either launch-on-shift or launch-on-capture scan testing. The flow of data and the warm-up controller operations keep the power supply rail voltage sufficiently charged for the fast launch-and-capture pulses.