Data shaping to reduce error rates in solid state memory devices
US10949119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Oct 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described for reducing error rates on data storage devices by applying data shaping to data written to such devices in order to avoid error-prone states on cells within the devices. Different states of individual cells (such as those representing different bit patterns) may have different propensities for error, and these propensities may vary during operation of a device. Thus, a device as disclosed herein may determine error-prone states for a cell or group of cells, and apply data shaping to data written to such cells to reduce the likelihood that writing the data places the cell or cells into an error-prone state. Data shaping may be used, for example, to increase the occurrence of “0” bits within input data, thus avoiding error-prone low voltage states that may be used to represent a series of “1” bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.