Using interleaved writes to separate die planes
US10949123B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Jun 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a solid state device includes a controller and a non-volatile memory. The non-volatile memory includes a plurality of dies. Each die includes a plurality of planes. A first super-plane-block is structured from a first plane of the plurality of dies. A second super-plane-block is structured from a second plane of the plurality of dies. A plurality of memory operation instructions that, when executed by the controller, cause the controller to receive a first data stream, write the first data stream to the first super-plane-block, receive a second data stream, and write the second data stream to the second super-plane-block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.