Data processor using a ring bus and method for controlling the same
US10949369B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2020 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Apr 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.