System, method, and computer program product for simultaneous routing and placement in an electronic circuit design
US10949596B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2020 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Jan 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments may include receiving an unplaced layout associated with an electronic circuit design and one or more grouping requirements. Embodiments may further include identifying instances that need to be placed at the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may also analyzing one or more instances that need to be placed at the unplaced layout and the one or more areas of the unplaced layout configured to receive the one or more instances. Embodiments may further include determining a location and an orientation for each of the one or more instances based upon, at least in part, the analyzing. Embodiments may also include generating a placed layout based upon, at least in part, the determined location and orientation for each of the one or more instances. Embodiments may further include during the generation of the placed layout, routing the placed layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.