Tunable memristor noise control
US10949738B1 · kind B1 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Oct 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memristor matrix comprising a crossbar array, a multiplexer and a noise control circuit. The noise control circuit may comprise a threshold comparator and a threshold feedback circuit to receive a first threshold and a second threshold and output a threshold signal based, in part, on an output of the threshold comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.