Shift register unit, gate driving circuit, display device and driving method
US10950320B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 8, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Aug 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0252
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit including a first output circuit configured to transfer a clock signal at a clock signal terminal to a signal output terminal as an output signal in response to a first node being at an active potential, a second output circuit configured to transfer the clock signal at the clock signal terminal to a carry output terminal as a carry output signal in response to the first node being at the active potential, and a delay circuit configured to generate a delayed version of a carry input signal in response to the carry input signal at a carry input terminal being active, and to transfer an inactive voltage at a first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.