Three dimensional semiconductor memory with residual memory layer
US10950612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Aug 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.