Method and circuit for current integration
US10951222B2 · kind B2 · utility
0Cited by
9References
15Claims
0Family size
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Key dates
| Filing date | Jul 4, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Jul 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/86
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.