Successive approximation register analog-to-digital converter with multiple sample capacitors
US10951225B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2020 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Mar 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC including a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.