Method and apparatus for ternary mapping
US10951230B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2020 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Mar 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a circuit for modulo-3 operation has an encoder stage coupled to a binary number, wherein the encoder stage includes one or more encoders, each one of the one or more encoders receives one or two binary bits of the binary number and generates a unary code of encoder. The circuit for modulo-3 operation further has one or more levels of reduction stage, wherein a first level of the one or more levels of reduction stage includes one or more mergers of first reduction, each one of the one or more mergers of first reduction receives two unary codes of encoder or a unary code of encoder and a bit from the binary number and generates a unary code of first reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.