Reusing switch ports for external buffer network
US10951549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.