Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment
US10956148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Nov 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.