Method of performing single event upset testing
US10956265B2 · kind B2 · utility
0Cited by
15References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2015 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Oct 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for simulating an event includes a memory system, a parity generator/validator, and a fault injector. The fault injector is configured to inject bits at an address in the memory system when the parity generator/validator is in an disabled state. A method of injecting a fault is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.