Method and apparatus for multiple accesses in memory and storage system, wherein the memory return addresses of vertexes that have not been traversed
US10956319B2 · kind B2 · utility
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Key dates
| Filing date | May 13, 2015 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | May 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method for multiple accesses in a memory, an apparatus supporting multiple accesses in the memory and a storage system. The method comprises: receiving a number N of addresses in the memory, wherein N is an integer larger than 1 and the number N of addresses are discontinuous; performing a preset operation according to the number N of addresses; and outputting the result of the operation. As a consequence, the performances of a computer system can be improved, and a user can input and use the desired addresses just as required by the user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.