Circuits and methods for compensating a mismatch in a sense amplifier
US10957366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | May 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.