Patent · US Active

Row based memory write assist and active sleep bias

US10957386B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zheng Guo · Portland, US
Clifford L. Ong · Portland, US
Eric A. Karl · Portland, US

Key dates

Filing date	Mar 23, 2020
Grant date	Mar 23, 2021
Priority date	—
Expiry date	Mar 23, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2227
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.