Frequency doubler pulse limiter and methods for limiting pulse widths produced by a frequency doubler
US10958255B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Dec 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.